The present invention relates to a successive approximation analog-to-digital converter, and in particular to a flash-successive approximation analog-to-digital converter for improving conversion speed by using both successive approximation conversion and flash conversion. So far, the conversion speed of analog-to-digital converter (hereinafter referred to ADC) has been reduced by improvement of the processing technique. The processing technique is classified into two classes: the successive approximation method having low speed and high resolution, and the flash method having high speed and low resolution.
An ADC using the successive approximation conversion, as shown in FIG. 1, comprises sample and holder(2), comparator(3), n bit successive approximation register(4) and n bit digital-to-analog converter(5) (hereinafter referred to DAC), and functions as follows.
The analog signal inputted through the input terminal(I) is sampled by sample and holder(2), compared with the signal outputted from n bit DAC(5) and inputted to an n bit successive approximation register (hereinafter referred to as SAR(4)).
The SAR(4) outputs in parallel the digital data corresponding to the reference voltages, and the DAC(5) converts the data into an analog signal. For example, if the SAR(4) outputs the data of "100 . . . 0", the n bit DAC(5) outputs the analog signal of Vref/2 (here, Vref is reference voltage) which is then compared with the sampled input signal by comparator(3).
If the sampled analog input signal is greater than Vref/2, the comparator(3) outputs a "1" and the most significant bit(MSB) of the output data of SAR(4) is set to "1". If the sampled analog input signal is less than Vref/2, the comparator outputs a "0" and the most significant bit (MSB) of the output data of SAR(4) is set to "0". In this manner the ADC determines the value of the MSB corresponding to the analog input signal.
Then in order to determine the next most significant bit the SAR(4) outputs "X100 . . . 0" (here, X is the pre-determined MSB whose value is set at "1" or "0". If the value of "X" is "1" the n-bit DAC(5) outputs 3/4 Vref. If the value of "X" is "0" the n-bit DAC(5) outputs 1/4 Vref. Again the output of n-bit DAC(5) is compared with the sampled analog input signal.
In this way, the input analog signal and the analog signal outputted from SAR(4) are compared with each other by comparator(3). If the sampled analog input signal is less than the output of DAC(5) the comparator outputs an "0" and the next most significant bit of the output data of SAR(4) is set to an "0". If the sampled analog input signal is greater than the output of DAC(5), the comparator outputs a "1" and the next significant bit of the output data of SAR(4) is set to a "1 ".
The SAR(4) will then output a "XX100 . . . " and the process will continue. If the above procedures are repeated to the least significant bit(LSB), the conversion is terminated and the SAR outputs the n-bit digital data corresponding to the input analog signal.
In the above, the number of bits represents the degree of resolution; the more the number of bits becomes, the more precise the converted digital data corresponding to the analog input signal will be.
Such successive approximation results in less error, but the conversion speed is comparatively slow.
FIG. 2 shows a block diagram for explaining a half flash A/D converter, which comprises sample and holder(7), n/2 bit flash A/D converter(8), latch(9), n/2 bit D/A converter(10), subtractor(11) and n/2 bit flash A/D converter(12). At first, the analog signal inputted through the input terminal(6) is sampled by sample and holder(7), and the sampled analog input signal is inputted to n/2 bit flash A/D converter(8). Flash converter (8) comprises 2.sup.n/2 comparators and an encoder, and the upper n/2 bits are determined at once. The digital data corresponding to the upper n/2 bits is latched into n/2 bit DAC(10) by latch (9), and the equivalent analog signal is determined. The analog signal which corresponds to the upper n/2 bits is subtracted from the analog input signal in subtractor(11).
This subtracted signal is further delivered to the other n/2 bit flash A/D converter(12), which determines the remaining lower n/2 bit digital data.
Such a half flash conversion is speedily made, but has a drawback is that a conversion error is generated while determining the lower n/2 bits.
Comparing the conversion time of the successive approximation A/D converter and the half-flash converter, the latter reduces the conversion time by 1 order of magnitude even though the number of bits increases (i.e. the resolution increases), because the number of bits does not affect the conversion time but only increases the number of comparators and encoders.
However, the conversion error is inversely proportional to conversion speed, and the successive approximation A/D converter has less conversion error than the half flash A/D converter.